 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| EN29F800 EN29F800 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 5.0 Volt-only FEATURES * 5.0V 10%, single power supply operation - Minimizes system level power requirements * Manufactured on 0.32 m process technology * High performance - Access times as fast as 45 ns * Low power consumption 25 mA typical active read current 30 mA typical program/erase current 1 A typical standby current (standard access time to active mode) - Sector erase time: 500ms typical - Chip erase time: 3.5s typical * Low Standby Current - 1A CMOS standby current-typical - 1mA TTL standby current * Low Power Active Current - 30mA active read current - 30mA program/erase current * JEDEC Standard program and erase commands * JEDEC standard DATA polling and toggle bits feature * Single Sector and Chip Erase * Sector Unprotect Mode * Embedded Erase and Program Algorithms * Erase Suspend / Resume modes: Read and program another Sector during Erase Suspend Mode * 0.32 m double-metal double-poly triple-well CMOS Flash Technology * Low Vcc write inhibit < 3.2V * >100K program/erase endurance cycle * Flexible Sector Architecture: - One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) - One 8 Kword, two 4 Kword, one 16 Kword and fifteen 32 Kword sectors (word mode) - Supports full chip erase - Individual sector erase supported - Sector protection: Hardware locking of sectors to prevent program or erase operations within individual sectors Additionally, temporary Sector Group Unprotect allows code changes in previously locked sectors. * High performance program/erase speed - Byte program time: 10s typical * 48-pin TSOP (Type 1) * Commercial Temperature Range GENERAL DESCRIPTION The EN29F800 is a 8-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 1,048,576 bytes or 524,288 words. Any byte can be programmed typically in 10s. The EN29F800 features 5.0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems. The EN29F800 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE) controls, which eliminate bus contention issues. This device is designed to allow either single (or multiple) Sector or full chip erase operation, where each Sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector. 4800 Great America Parkway, Suite 202 1 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 CONNECTION DIAGRAMS A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# 18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 Standard TSOP TABLE 1. PIN DESCRIPTION Pin Name A0-A19 DQ0-DQ14 DQ15 / A-1 Function Addresses 15 Data Inputs/Outputs DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) Chip Enable Output Enable Hardware Reset Pin Ready/Busy Output Write Enable Supply Voltage (5V 10% ) Ground Internally connected pin FIGURE 1. LOGIC DIAGRAM EN29F800 19 A0 - A18 DQ0 - DQ15 (A-1) Reset CE OE WE Byte RY/BY 16 or 8 CE OE Reset RY/BY WE Vcc Vss NC 4800 Great America Parkway, Suite 202 2 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE Sect or ADDRESS RANGE (X16) 7E000h-7FFFFh 7D000h-7DFFFh 7C000h-7CFFFh 78000h-7BFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-6FFFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 00000h-07FFFh SECTOR SIZE (Kbytes / Kwords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 A18 A17 A16 A15 A14 A13 A12 (X8) FC000h-FFFFFh FA000h-FBFFFh F8000h-F9FFFh F0000h - F7FFFh E0000h - EFFFFh D0000h - DFFFFh C0000h - CFFFFh B0000h - BFFFFh A0000h - AFFFFh 90000h - 9FFFFh 80000h - 8FFFFh 70000h - 7FFFFh 60000h - 6FFFFh 50000h - 5FFFFh 40000h - 4FFFFh 30000h - 3FFFFh 20000h - 2FFFFh 10000h - 1FFFFh 00000h - 0FFFFh 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 X X X X X X X X X X X X X X X 1 0 0 X X X X X X X X X X X X X X X X X 1 0 X X X X X X X X X X X X X X X X 4800 Great America Parkway, Suite 202 3 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE Sect or ADDRESS RANGE (X16) 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh 03000h-03FFFh 02000h-02FFFh 00000h-01FFFh SECTOR SIZE (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 A18 A17 A16 A15 A14 A13 A12 (X8) F0000h - FFFFFh E0000h - EFFFFh D0000h - DFFFFh C0000h - CFFFFh B0000h - BFFFFh A0000h - AFFFFh 90000h - 9FFFFh 80000h - 8FFFFh 70000h -7FFFFh 60000h - 6FFFFh 50000h - 5FFFFh 40000h - 4FFFFh 30000h - 3FFFFh 20000h - 2FFFFh 10000h - 1FFFFh 08000h - 0FFFFh 06000h - 07FFFh 04000h - 05FFFh 00000h - 01FFFh 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 X X X X X X X X X X X X X X X 1 0 0 0 X X X X X X X X X X X X X X X X 1 1 0 X X X X X X X X X X X X X X X X 1 0 X 4800 Great America Parkway, Suite 202 4 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 PRODUCT SELECTOR GUIDE Product Number Speed Option Vcc=5.0V 10% -45 45 45 25 -55 55 55 30 EN29F800 -70 70 70 30 -90 90 90 35 Max Access Time, ns (tacc) Max CE# Access, ns (tce) Max OE# Access, ns (toe) BLOCK DIAGRAM Vcc Vss RY/BY Block Protect Switches DQ0-DQ15 (A-1) Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic STB Input/Output Buffers WE Command Register CE OE Data Latch Y-Decoder Address Latch STB Y-Gating Vcc Detector Timer X-Decoder Cell Matrix A0-A18 4800 Great America Parkway, Suite 202 5 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 TABLE 3. OPERATING MODES 8M FLASH USER MODE TABLE Operation Read Write CMOS Standby TTL Standby Output Disable Hardware Reset Temporary Sector Unprotect CE# L L Vcc 0.5V H L X X OE# L H X X H X X WE # H L X X H X X Reset# H H Vcc 0.5V H H L VID A0A18 AIN AIN X X X X AIN DQ0-DQ7 DOUT DIN High-Z High-Z High-Z High-Z DIN DQ8-DQ15 Byte# Byte# = VIL = VIH DOUT High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DIN X Notes: L=logic low= VIL, H=Logic High= VIH, VID =11.0 0.5V, X=Don't Care, DIN=Data In, DOUT=Data Out, AIN=Address In TABLE 4. DEVICE IDENTIFICTION 8M FLASH MANUFACTURER/DEVICE ID TABLE Description Mode CE L L L L L L OE L L L L L L WE H H H H H H A18 to A12 X X X A11 to A10 X X X A9 A8 A7 A6 A5 to A2 X X X A1 A0 DQ8 to DQ15 X 22h X 22h X X X L X H L X DQ7 to DQ0 1Ch 89h 89h 8Ah 8Ah 01h (Unprotected) Manufacturer ID: EON Device ID Word (top boot block) VID VID VID H H H 1 X X X L L L L L L L H H 1 Byte Word Byte Device ID (bottom boot block) 1 Sector Protection Verification SA X VID H 1 00h (Protected) Note: 1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be read with A8=H. 2. If a device ID is read with A8=L, the chip will output configuration code 7Fh. A further Device ID must be read with A8=H. 4800 Great America Parkway, Suite 202 6 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 USER MODE DEFINITIONS Word / Byte Configuration The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic `1', then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#. On the other hand, if the Byte# Pin is set at logic `0', then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Standby Mode The EN29F800 has a CMOS-compatible standby mode, which reduces the current to < 1A (typical). It is placed in CMOS-compatible standby when the CE pin is at VCC 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE pin is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE input. Read Mode The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" additional details. Output Disable Mode When the CE or OE pin is at a logic high level (VIH), the output from the EN29F800 is disabled. The output pins are placed in a high impedance state. Auto Select Identification Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. 4800 Great America Parkway, Suite 202 7 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. Write Mode Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The Command Definitions in Table 5 show the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, which can be obtained by contacting a representative of Eon Silicon Devices, Inc. Temporary Sector Unprotect Start This feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sectgor addresses. Once is removed from the RESET# pin, all the previously protected sector are protected again. See accompanying figure and timing diagrams for more details. Notes: 1. All protected sectors unprotected. 2. Previously protected sectors protected again. Reset#=VID (note 1) Perform Erase or Program Operations Reset#=VIH Temporary Sector Unprotect Completed (note 2) 4800 Great America Parkway, Suite 202 8 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Hardware Data protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise. Low VCC Write Inhibit When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO. Write Pulse "Glitch" protection Noise pulses of less than 5 ns (typical) on OE , CE or W E do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of CE = VIH, or W E = VIH. To initiate a write cycle, CE and W E must be a logical zero. If CE , W E , and OE are all logical zero (not recommended usage), it will be considered a write. Power-up Write Inhibit During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of WE. 4800 Great America Parkway, Suite 202 9 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 COMMAND DEFINITIONS The operations of the EN29F800 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode. Table 5. EN29F800 Command Definitions Bus Cycles Command Sequence Read Reset Manufacturer ID Device ID Top Boot Autoselect Cycles 1 st 2 nd 3 rd 4 th 5 th 6 th Write Cycle Add Data Write Cycle Add Data Write Cycle Add Data Write Cycle Add Data Write Cycle Add Data Write Cycle Add Data 1 1 Word Byte Word 4 Byte Word 4 Byte Word 4 Byte Word Byte Word Byte Word Byte 4 6 6 1 1 4 RA xxx 555 AAA 555 RD F0 AA 2AA 555 2AA AA 55 555 2AA AA 55 555 2AA AA 55 555 AA AA AA B0 30 2AA 555 2AA 555 2AA 555 55 55 55 AAA 555 AAA 555 AAA 555 AAA A0 80 80 AAA 555 90 AAA 555 90 55 555 AAA 555 90 90 000/ 100 001/ 101 002/ 102 001/ 101 002/ 102 (SA) X02 (SA) X04 PA 555 AAA 555 AAA 7F/ 1C 7F/ 2289 7F/ 89 7F/ 228A 7F/ 8A XX00 XX01 00 01 PD AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA xxx xxx Device ID Bottom Boot Sector Protect Verify Program Chip Erase Sector Erase Erase Suspend Erase Resume Address and Data values indicated in hex RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don't-Care. PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A12 uniquely select any Sector. Reading Array Data The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset. 4800 Great America Parkway, Suite 202 10 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don'tcare for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This is an alternative method which is intended for PROM programmers and requires VID on address bit A9. Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at any address any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data. Word / Byte Programming Command The device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN29F800 is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE or W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is first. Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can return the device to Read mode. Chip Erase Command Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. 4800 Great America Parkway, Suite 202 11 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Erase Suspend / Resume Command The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don't-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The Autoselect command is not supported during Erase Suspend Mode. The system must write the Erase Resume command (address bits are don't-care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. 4800 Great America Parkway, Suite 202 12 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 WRITE OPERATION STATUS DQ7 DATA Polling The EN29F800 provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations. The DATA Polling feature is active during the Byte Programming, Sector Erase, Chip Erase, Erase Suspend. (See Table 6) When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming, DATA polling is valid after the rising edge of the fourth WE or C E pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse. DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address used is in a protected sector. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing diagram is shown in Figure 8. RY/BY: Ready/Busy The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc. In the output is low, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. DQ6 Toggle Bit I The EN29F800 provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling OE or CE ) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be 4800 Great America Parkway, Suite 202 13 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase W E pulse. In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected blocks are protected, DQ6 will toggle for about 100 s. The chip will then return to the read mode without changing data in all protected blocks. Toggling either CE or OE will cause DQ6 to toggle. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9. DQ5 Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a "1" on DQ5. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3 Sector Erase Timer After writing a sector erase command sequence, the output on DQ3 can be used to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) When sector erase starts, DQ3 switches from "0" to "1." This device does not support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a "1" after the first 30h command. Future devices may support this feature. DQ2 Erase Toggle Bit II The "Toggle Bit" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. 4800 Great America Parkway, Suite 202 14 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6). Write Operation Status Operation Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend Program DQ7 DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No Toggle Data Toggle DQ5 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 No toggle Toggle Toggle Data N/A RY/BY # 0 0 1 1 0 Erase Suspend Mode 4800 Great America Parkway, Suite 202 15 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Table 6. Status Register Bits DQ Name Logic Level `1' Definition Erase Complete or erase Sector in Erase suspend Erase On-Going Program Complete or data of non-erase Sector during Erase Suspend Program On-Going Erase or Program On-going Read during Erase Suspend Erase Complete Program or Erase Error Program or Erase On-going Erase operation start Erase timeout period on-going Chip Erase, Erase or Erase suspend on currently addressed Sector. (When DQ5=1, Erase Error due to currently addressed Sector. Program during Erase Suspend ongoing at current address Erase Suspend read on non Erase Suspend Sector 7 DATA POLLING `0' DQ7 DQ7 `-1-0-1-0-1-0-1-' DQ6 `-1-1-1-1-1-1-1-` 6 TOGGLE BIT 5 3 ERROR BIT ERASE TIME BIT `1' `0' `1' `0' 2 TOGGLE BIT `-1-0-1-0-1-0-1-' DQ2 Notes: DQ7 DATA Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5 Error Bit: set to "1" if failure in programming or erase DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector. 4800 Great America Parkway, Suite 202 16 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 EMBEDDED ALGORITHMS Flowchart 1. Embedded Program START Write Program Command Sequence (shown below) Data Poll Device Verify Data? Increment Address No Last Address? Yes Programming Done Flowchart 2. Embedded Program Command Sequence See the Command Definitions section for more information. 555H / AAH 2AAH / 55H 555H / A0H PROGRAM ADDRESS / PROGRAM DATA 4800 Great America Parkway, Suite 202 17 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Flowchart 3. Embedded Erase START Write Erase Command Sequence Data Poll from System or Toggle Bit successfully completed Data =FFh? No Yes Erase Done 4800 Great America Parkway, Suite 202 18 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Flowchart 4. Embedded Erase Command Sequence See the Command Definitions section for more information. Chip Erase Sector Erase 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 555H/80H 555H/80H 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 555H/10H Sector Address/30H 4800 Great America Parkway, Suite 202 19 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Flowchart 5. DATA Polling Algorithm Start Read Data DQ7 = Data? No No DQ5 = 1? Yes Read Data Yes DQ7 = Data? No Fail Yes Pass Flowchart 6. Toggle Bit Algorithm Start Read Data No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Data DQ6 = Toggle? Yes Fail No Pass 4800 Great America Parkway, Suite 202 20 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Table 7. DC Characteristics (Ta = 0C to 70C or - 40C to 85C; VCC = 5.0V 10%) Symbol ILI ILO ICC1 Parameter Input Leakage Current Output Leakage Current Supply Current (read) TTL (read) CMOS Byte (read) CMOS Word Supply Current (Standby - TTL) Test Conditions 0V VIN Vcc 0V VOUT Vcc Min Typ Max 5 5 Unit A A mA mA mA mA A mA V V V V V 19 CE# = VIL; OE# = VIH; f = 5MHz CE# = VIH BYTE# = RESET# = CE# = Vcc 0.2V Byte program, Sector or Chip Erase in progress -0.5 2 IOL = 2 mA IOH = -2.5 mA IOH = -100 A 2.4 Vcc 0.4V 10.5 20 28 0.4 0.3 30 30 40 50 1.0 5.0 60 0.8 Vcc 0.5 0.45 ICC2 ICC3 VIL VIH VOL VOH VID IID VLKO (Standby - CMOS) (1) Supply Current (Program or Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply voltage (Erase and Program lock-out) 11.5 100 V A V A9 = VID 3.2 4.2 Notes: (1) BYTE# and RESET# pin input buffers are always enabled so that they draw power if not at full CMOS supply voltages 4800 Great America Parkway, Suite 202 21 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Test Conditions 5.0 V 2.7 k Device Under Test CL 6.2 k Note: Diodes are IN3064 or equivalent Test Specifications Test Conditions Output Load Output Load Capacitance, CL Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0-0.3 1.5 1.5 -45 -55 30 5 0.0-0.3 1.5 1.5 -70 100 20 0.45-2.4 0.8, 2.0 0.8, 2.0 -90 100 20 0.45-2.4 0.8, 2.0 0.8, 2.0 Unit pF ns V V V 1 TTL Gate 4800 Great America Parkway, Suite 202 22 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 AC CHARACTERISTICS Hardware Reset (Reset#) Parameter Std tREADY tREADY tRP tRH Description Reset# Pin Low to Read or Write Embedded Algorithms Reset# Pin Low to Read or Write Non Embedded Algorithms Reset# Pulse Width Reset# High Time Before Read Test Setup Max Max Min Min Speed options -45 -55 -70 -90 20 500 500 50 Unit s ns ns ns Reset# Timings RY/BY# 0V CE# OE# tRH RESET# tRP tREADY Reset Timings NOT During Automatic Algorithms RY/BY# tREADY CE# OE# RESET# tRP tRH Reset Timings During Automatic Algorithms 4800 Great America Parkway, Suite 202 23 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 AC CHARACTERISTICS Word / Byte Configuration (Byte#) Std Parameter tELFL/tELFH tFLQZ tFHQV Speed Description CE# to Byte# switching Low or High Byte# switching Low to Output HIGH Z Byte# switching High to Output Active Max Max Min -45 0 20 45 -55 0 20 55 -70 0 20 70 -90 0 20 90 -120 0 30 120 Unit ns ns ns CE OE Byte Switching from word to byte mode tELFL Data Output (DQ0-DQ7) Data Output (DQ0-DQ14) DQ0-DQ14 DQ15 / A-1 tELFH tFLQZ DQ15 Output Address Input Byte Switching from byte to word mode DQ0-DQ14 Data Output (DQ0-DQ7) Data Output (DQ0-DQ14) DQ15 / A-1 Address Input tFHQV DQ15 Output Byte timings for Read Operations CE The falling edge of the last WE signal WE BYTE tSET tHOLD Byte timings for Read Operations 4800 Great America Parkway, Suite 202 24 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Table 8. AC CHARACTERISTICS Read-only Operations Characteristics Parameter Symbols JEDEC Standard Description Read Cycle Time Address to Output Delay Chip Enable To Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE or OE , whichever occurs first Notes: For - 50 Vcc = 5.0V 5% Output Load : 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V Vcc = 5.0V 10% Output Load: 1 TTL gate and 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V Test Setup Min Speed Options -45 45 45 45 25 20 20 0 -55 55 55 55 30 20 20 0 -70 70 70 70 30 20 20 0 -90 90 90 90 35 20 20 0 Unit ns ns ns ns ns ns ns tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH CE = VIL OE = VIL Max Max Max Max Max Min OE = VIL For all others: tRC Addresses Addresses Stable tACC CE# tDF tOE OE# tOEH WE# tCE Output Valid tOH HIGH Z Outputs Reset# RY/BY# 0V Figure 5. AC Waveforms for READ Operations 4800 Great America Parkway, Suite 202 25 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Table 9. AC CHARACTERISTICS Write (Erase/Program) Operations Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and DATA Polling Read Recovery Time before Min Min Min Min Min Min MIn Min Min Min Min Min Min Typ Max -45 45 0 35 20 0 0 0 10 0 0 0 25 20 7 200 0.3 5 3 35 50 500 Speed Options -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 200 0.3 5 3 35 50 500 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 200 0.3 5 3 35 50 500 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 200 0.3 5 3 35 50 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s ns tAVAV tAVWL tWLAX tDVWH tWHDX tWC tAS tAH tDS tDH tOES tOEH tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1 tGHWL tCS tCH tWP tWPH tWHWH1 Write ( OE High to W E Low) CE SetupTime CE Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Word AND Byte Mode) tWHWH2 tWHWH3 tWHWH2 tWHWH3 tVCS tVIDR Sector Erase Operation Typ Max Chip Erase Operation Typ Max Vcc Setup Time Rise Time to VID Min Min 4800 Great America Parkway, Suite 202 26 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE Controlled Writes Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Min Min Min Min Min Min 0 10 Min Min Min Min Min Typ -45 45 0 35 20 0 0 0 10 0 0 0 25 20 7 Speed Options -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s tAVAV tAVEL tELAX tDVEH tEHDX tWC tAS tAH tDS tDH tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tWS tWH tCP tCPH Toggle and Data Polling Read Recovery Time before Write ( OE High to CE Low) W E SetupTime W E Hold Time Write Pulse Width Write Pulse Width High Programming Operation (byte AND word mode) tWHWH1 tWHWH1 Max 200 0.3 5 3 35 50 500 200 0.3 5 3 35 50 500 200 0.3 5 3 35 50 500 200 0.3 5 3 35 50 500 s s s s s s ns tWHWH2 tWHWH2 tWHWH3 tWHWH3 tVCS tVIDR Sector Erase Operation Typ Max Chip Erase Operation Typ Max Vcc Setup Time Rise Time to VID Min Min 4800 Great America Parkway, Suite 202 27 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Table 11. ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time Byte Word Typ 1 19 7 7 8.2 4.1 100K Limits Max 8 35 300 300 24.5 12.2 cycles Minimum 100K cycles guaranteed Unit sec sec s s sec Excludes system level overhead Comments Excludes 00H programming prior to erasure Erase/Program Endurance Table 12. LATCH UP CHARACTERISTICS Parameter Description Input voltage with respect to V ss on all pins except I/O pins (including A9, Reset and OE ) Input voltage with respect to V ss on all I/O Pins Vcc Current Min -1.0 V -1.0 V -100 mA Max 12.0 V Vcc + 1.0 V 100 mA Note : These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits. Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25C, 1.0MHz Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Table 15. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years 4800 Great America Parkway, Suite 202 28 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 SWITCHING WAVEFORMS Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings Erase Command Sequence (last 2 cycles) tWC tAS tAH Read Status Data (last two cycles) Addresses 0x2AA SA 0x555 for chip erase VA VA CE# tGHWL OE# tWP tCH WE# tCS tWPH tWHWH2 or tWHWH3 Data 0x55 tDS 0x30 0x555 for chip erase tDH tBUSY Status DOUT tRB RY/BY# VCC tVCS Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence. 4800 Great America Parkway, Suite 202 29 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Figure 7. Program Operation Timings Program Command Sequence (last 2 cycles) tWC tAS tAH Program Command Sequence (last 2 cycles) Addresses 0x555 PA PA PA CE# tGHWL OE# tWP tCH WE# tCS tWPH tWHWH1 Data tDS OxA0 PD Status DOUT tRB tDH tBUSY RY/BY# tVCS VCC Notes: 1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address. 2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence. 4800 Great America Parkway, Suite 202 30 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm Operations tRC Addresses tCH VA tACC tCE VA VA CE# tOE OE# tOEH tDF WE# tOH DQ[7] Complement Complement True Valid Data DQ[6:0] tBUSY Status Data Status Data True Valid Data RY/BY# Notes: 1. VA=Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle. Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm Operations tRC Addresses tCH VA tACC tCE VA VA VA CE# tOE OE# tOEH tDF WE# tOH DQ6, DQ2 tBUSY Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data RY/BY# 4800 Great America Parkway, Suite 202 31 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 AC CHARACTERISTICS Enter Embedded Erase Erase Suspend Enter Erase Suspend Program Enter Suspend Read Enter Suspend Program Erase Resume WE# Erase Erase Suspend Read Erase Erase Complete DQ6 DQ2 DQ2 vs. DQ6 Temporary Sector Unprotect Parameter Std tVIDR tRSP Description VID Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect Min Min Speed Option -55 -70 500 4 Unit Ns s -45 -90 Temporary Sector Unprotect Timing Diagram VID RESET# 0 or 5V 0 or 5 V tVIDR tVIDR CE# WE# tRSP RY/BY# 4800 Great America Parkway, Suite 202 32 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Figure 10. Alternate CE# Controlled Write Operation Timings 0x555 for Program 0x2AA for Erase PA for Program SA for Sector Erase 0x555 for Chip Erase Addresses tWC WE# tGHEL OE# tWS CE# tDS Data 0xA0 for Program 0x55 for Erase PD for Program 0x30 for Sector Erase 0x10 for Chip Erase VA tAS tAH tWH tCP tCPH tCWHWH1 / tCWHWH2 / tCWHWH3 tDH tBUSY Status DOUT RY/BY# tRH Reset# Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last staus read cycle Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence. 4800 Great America Parkway, Suite 202 33 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 FIGURE 4. TSOP 4800 Great America Parkway, Suite 202 34 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 4800 Great America Parkway, Suite 202 35 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit Current 1 Value -65 to +125 -65 to +125 -55 to +125 200 2 Unit C C C mA V A9, OE#, Reset# Voltage with Respect to Ground 3 -0.5 to +11.5 All other pins -0.5 to Vcc+0.5 V Vcc -0.5 to +7.0 V Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9, OE#, RESET# pins is -0.5V. During voltage transitions, A9, OE#, RESET# pins may undershoot Vss to -1.0V for periods of up to 50ns and to -2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot Vss to -1.0V for periods of up to 50ns and to -2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. RECOMMENDED OPERATING RANGES1 Parameter Ambient Operating Temperature Commercial Devices Industrial Devices Operating Supply Voltage Vcc for 5% devices Vcc for 10% devices 1. Value 0 to 70 -40 to 85 Unit C 4.75 to 5.25 4.5 to 5.5 V Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed. Maximum Negative Overshoot Waveform 4800 Great America Parkway, Suite 202 36 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Maximum Positive Overshoot Waveform Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 ORDERING INFORMATION EN29F800 T 45 T I TEMPERATURE RANGE (Blank) = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE T = 48-pin TSOP S = Small Outline Package SPEED 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector BASE PART NUMBER EN = EON Silicon Devices 29F = FLASH, 5V Read Program Erase 800 = 8 Megabit (1024K x 8 / 512 x 16) 4800 Great America Parkway, Suite 202 37 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 EN29F800 Revisions List A,B,C: Preliminary D (2001.07.03): Table 7. Icc2 is with BYTE# and RESET# pin at full CMOS levels Pg. 9 Logical Inhibit section now says that if CE , W E , and OE are all logical zero (not recommended usage), it will be considered a write. VID is everywhere changed to be VID =11.5 0.5V E (2001.07.05): "block" changed to "sector" LACTHUP >= 200mA line removed from first page Deleted Sector Un/Protect flowcharts Chip erase and Sector Erase command descriptions modified. DQ7,DQ5,DQ3 status polling descriptions modified. Table 12 Latchup characteristics modified Changed P/E endurance to 100K everywhere Changed Absolute Maximum Ratings 4800 Great America Parkway, Suite 202 38 Santa Clara, CA 95054 Rev. E, Issue Date: 2001/07/05 Tel: 408-235-8680 Fax: 408-235-8685 |
Price & Availability of EN29F800T90TI
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |